1/9 april 2001 STB40NF10L n-channel 100v - 0.028 w - 40a d2pak low gate charge stripfet? power mosfet (1) starting t j = 25 c, i d = 20a, v dd = 40v n typical r ds (on) = 0.028 w n exceptional dv/dt capability n 100% avalanche tested n application oriented characterization n add suffix t4 for ordering in tape & reel description this power mosfet series realized with stmicro- electronics unique stripfet process has specifical- ly been designed to minimize input capacitance and gate charge. it is therefore suitable as primary switch in advanced high-efficiency isolated dc-dc converters for telecom and computer application. it is also intended for any application with low gate charge drive requirements. applications n high-efficiency dc-dc converters n ups and motor control n automotive absolute maximum ratings ( l ) pulse width limited by safe operating area type v dss r ds(on) i d STB40NF10L 100 v < 0.033 w 40 a symbol parameter value unit v ds drain-source voltage (v gs = 0) 100 v v dgr drain-gate voltage (r gs = 20 k w ) 100 v v gs gate- source voltage 15 v i d drain current (continuos) at t c = 25c 40 a i d drain current (continuos) at t c = 100c 25 a i dm ( l ) drain current (pulsed) 160 a p tot total dissipation at t c = 25c 150 w derating factor 1 w/c e as (1) single pulse avalanche energy 430 mj t stg storage temperature C65 to 175 c t j max. operating junction temperature 175 c d2pak 1 3 internal schematic diagram
STB40NF10L 2/9 thermal data electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic rthj-case thermal resistance junction-case max 1 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 100 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 10 a i gss gate-body leakage current (v ds = 0) v gs = 15v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250a 1 1.7 2.5 v r ds(on) static drain-source on resistance v gs = 10v, i d = 20 a 0.028 0.033 w v gs = 5v, i d = 20 a 0.030 0.036 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds = 15v , i d = 20 a 25 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs = 0 2300 pf c oss output capacitance 290 pf c rss reverse transfer capacitance 125 pf
3/9 STB40NF10L electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 50 v, i d = 20 a r g = 4.7 w v gs = 4.5v (see test circuit, figure 3) 25 ns t r rise time 82 ns q g total gate charge v dd = 80v, i d =40a,v gs = 5v 46 64 nc q gs gate-source charge 12 nc q gd gate-drain charge 22 nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off-delay time fall time v dd = 50 v, i d = 20 a, r g =4.7 w, v gs = 4.5v (see test circuit, figure 3) 64 24 ns ns t d(off) t f t c off-voltage rise time fall time cross-over time vclamp =80v, i d = 40 a r g =4.7 w, v gs = 4.5v (see test circuit, figure 3) 51 29 53 ns ns ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 40 a i sdm (1) source-drain current (pulsed) 160 a v sd (2) forward on voltage i sd = 40 a, v gs = 0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 40 a, di/dt = 100a/s, v dd = 30v, t j = 150c (see test circuit, figure 5) 110 467 8 ns nc a safe operating area thermal impedance
STB40NF10L 4/9 transfer characteristics gate charge vs gate-source voltage static drain-source on resistance transconductance output characteristics capacitance variations
5/9 STB40NF10L normalized gate threshold voltage vs temperature source-drain diode forward characteristics normalized on resistance vs temperature normalized drain-source breakdown vs temperature
STB40NF10L 6/9 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
7/9 STB40NF10L 1 dim. mm. inch min. typ max. min. typ. max. a 4.4 4.6 0.173 0.181 a1 2.49 2.69 0.098 0.106 a2 0.03 0.23 0.001 0.009 b 0.7 0.93 0.027 0.036 b2 1.14 1.7 0.044 0.067 c 0.45 0.6 0.017 0.023 c2 1.23 1.36 0.048 0.053 d 8.95 9.35 0.352 0.368 d1 8 0.315 e 10 10.4 0.393 e1 8.5 0.334 g 4.88 5.28 0.192 0.208 l 15 15.85 0.590 0.625 l2 1.27 1.4 0.050 0.055 l3 1.4 1.75 0.055 0.068 m 2.4 3.2 0.094 0.126 r 0.4 0.015 v2 0 o8o d 2 pak mechanical data 3
STB40NF10L 8/9 tape and reel shipment (suffix t4)* tube shipment (no suffix)* d 2 pak footprint * on sales type dim. mm inch min. max. min. max. a 330 12.992 b 1.5 0.059 c 12.8 13.2 0.504 0.520 d 20.2 0795 g 24.4 26.4 0.960 1.039 n 100 3.937 t 30.4 1.197 base qty bulk qty 1000 1000 reel mechanical data dim. mm inch min. max. min. max. a0 10.5 10.7 0.413 0.421 b0 15.7 15.9 0.618 0.626 d 1.5 1.6 0.059 0.063 d1 1.59 1.61 0.062 0.063 e 1.65 1.85 0.065 0.073 f 11.4 11.6 0.449 0.456 k0 4.8 5.0 0.189 0.197 p0 3.9 4.1 0.153 0.161 p1 11.9 12.1 0.468 0.476 p2 1.9 2.1 0.075 0.082 r50 1.574 t 0.25 0.35 0.0098 0.0137 w 23.7 24.3 0.933 0.956 tape mechanical data
9/9 STB40NF10L information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectroni cs. specifi cation mentio ned in this publication are subject to change without notice. this publication supersedes and replaces all in formation previou sly supplied. stmicroel ectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a trademark of stmicroelectronics ? 2001 stmicroelectronics C pr inted in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malay sia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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